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NCP5106A, NCP5106B High Voltage, High and Low Side Driver
The NCP5106 is a high voltage gate driver IC providing two outputs for direct drive of 2 N-channel power MOSFETs or IGBTs arranged in a half-bridge configuration version B or any other high-side + low-side configuration version A. It uses the bootstrap technique to ensure a proper drive of the high-side power switch. The driver works with 2 independent inputs.
Features http://onsemi.com MARKING DIAGRAMS
1 SOIC-8 D SUFFIX CASE 751 8 5106x ALYW G
* * * * * * * * * * * * * * * *
High Voltage Range: Up to 600 V dV/dt Immunity 50 V/nsec Negative Current Injection Characterized Over the Temperature Range Gate Drive Supply Range from 10 V to 20 V High and Low Drive Outputs Output Source / Sink Current Capability 250 mA / 500 mA 3.3 V and 5 V Input Logic Compatible Up to VCC Swing on Input Pins Extended Allowable Negative Bridge Pin Voltage Swing to -10 V for Signal Propagation Matched Propagation Delays Between Both Channels Outputs in Phase with the Inputs Independent Logic Inputs to Accommodate All Topologies (Version A) Cross Conduction Protection with 100 ns Internal Fixed Dead Time (Version B) Under VCC LockOut (UVLO) for Both Channels Pin-to-Pin Compatible with Industry Standards These are Pb-Free Devices
1
1 PDIP-8 P SUFFIX CASE 626 NCP5106 x A L or WL Y or YY W or WW G or G
NCP5106x AWLG YYWW
= Specific Device Code = A or B version = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PINOUT INFORMATION VCC IN_HI IN_LO GND 1 2 3 4 8 7 6 5 VBOOT DRV_HI BRIDGE DRV_LO
Typical Applications
* Half-Bridge Power Converters * Any Complementary Drive Converters (Asymmetrical Half-Bridge, *
Active Clamp) (A Version Only). Full-Bridge Converters
8 Pin Package
ORDERING INFORMATION
Device NCP5106APG NCP5106ADR2G NCP5106BPG NCP5106BDR2G Package PDIP-8 (Pb-Free) Shipping 50 Units / Rail
SOIC-8 2500 / Tape & Reel (Pb-Free) PDIP-8 (Pb-Free) 50 Units / Rail
SOIC-8 2500 / Tape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2010
March, 2010 - Rev. 5
1
Publication Order Number: NCP5106/D
NCP5106A, NCP5106B
Vbulk + C1 D4 C3 GND NCP1395 Q1 U1 8 VBOOT Vcc 2 7 IN_HI DRV_HI 3 6 IN_LO Bridge 4 5 GND DRV_LO 1 NCP5106 GND GND D3 GND U2 R1 C4 Lf D2 Q2 C6 T1 D1 L1 + Out+ C3 Out-
GND Vcc
GND
Figure 1. Typical Application Resonant Converter (LLC type)
Vbulk
+
C1 D4 C3 GND 1 2 3 4 Q1 U1 8 VBOOT Vcc 7 IN_HI DRV_HI 6 IN_LO Bridge 5 GND DRV_LO NCP5106 GND C4 C5 T1 D1 L1 + Out+ C3 Out- D2 Q2 C6
GND Vcc
MC34025
GND
GND D3 GND U2
R1
Figure 2. Typical Application Half Bridge Converter
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2
NCP5106A, NCP5106B
VCC IN_HI PULSE TRIGGER LEVEL SHIFTER SQ RQ UV DETECT DRV_HI VCC UV DETECT VBOOT
GND
GND
BRIDGE VCC
IN_LO
DELAY
DRV_LO GND
GND
GND
GND
GND
Figure 3. Detailed Block Diagram: Version A
VCC IN_HI
VCC
UV DETECT PULSE TRIGGER LEVEL SHIFTER SQ RQ UV DETECT
VBOOT
DRV_HI
GND
CROSS CONDUCTION PREVENTION
GND
BRIDGE VCC
IN_LO
DELAY
DRV_LO GND
GND
GND
Figure 4. Detailed Block Diagram: Version B
PIN DESCRIPTION
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IN_HI Logic Input for High Side Driver Output in Phase Logic Input for Low Side Driver Output in Phase Ground IN_LO GND DRV_LO VCC Low Side Gate Drive Output Low Side and Main Power Supply Bootstrap Power Supply VBOOT DRV_HI High Side Gate Drive Output BRIDGE Bootstrap Return or High Side Floating Supply Return
Pin Name
Description
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NCP5106A, NCP5106B
MAXIMUM RATINGS
Rating VCC VCC_transient VBRIDGE VBRIDGE VBOOT-VBRIDGE VDRV_HI VDRV_LO dVBRIDGE/dt VIN_XX Main power supply voltage Main transient power supply voltage: IVCC_max = 5 mA during 10 ms VHV: High Voltage BRIDGE pin Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO (see characterization curves for detailed results) VHV: Floating supply voltage VHV: High side output voltage Low side output voltage Allowable output slew rate Inputs IN_HI, IN_LO ESD Capability: - HBM model (all pins except pins 6-7-8 in 8 pins package or 11-12-13 in 14 pins package) - Machine model (all pins except pins 6-7-8 in 8 pins package or 11-12-13 in 14 pins package) Latch up capability per JEDEC JESD78 RqJA Power dissipation and Thermal characteristics PDIP-8: Thermal Resistance, Junction-to-Air SO-8: Thermal Resistance, Junction-to-Air Storage Temperature Range Maximum Operating Junction Temperature 100 178 -55 to +150 +150 C/W Symbol Value -0.3 to 20 23 -1 to 600 -10 -0.3 to 20 VBRIDGE - 0.3 to VBOOT + 0.3 -0.3 to VCC + 0.3 50 -1.0 to VCC + 0.3 2 200 Unit V V V V V V V V/ns V kV V
TST TJ_max
C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NCP5106A, NCP5106B
ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, -40C < TJ < 125C, Outputs loaded with 1 nF)
TJ -40C to 125C Rating OUTPUT SECTION Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1) Output low short circuit pulsed current VDRV = VCC, PW v 10 ms (Note 1) Output resistor (Typical value @ 25C) Source Output resistor (Typical value @ 25C) Sink High level output voltage, VBIAS-VDRV_XX @ IDRV_XX = 20 mA Low level output voltage VDRV_XX @ IDRV_XX = 20 mA DYNAMIC OUTPUT SECTION Turn-on propagation delay (Vbridge = 0 V) Turn-off propagation delay (Vbridge = 0 V or 50 V) (Note 2) Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load Output voltage fall time (from 90% to 10% @VCC = 15 V) with 1 nF load Propagation delay matching between the High side and the Low side @ 25C (Note 3) Internal fixed dead time (only valid for B version) (Note 4) Minimum input width that changes the output Maximum input width that does not change the output INPUT SECTION Low level input voltage threshold Input pull-down resistor (VIN < 0.5 V) High level input voltage threshold Logic "1" input bias current @ VIN_XX = 5 V @ 25C Logic "0" input bias current @ VIN_XX = 0 V @ 25C SUPPLY SECTION VCC UV Start-up voltage threshold VCC UV Shut-down voltage threshold Hysteresis on VCC Vboot Start-up voltage threshold reference to bridge pin (Vboot_stup = Vboot - Vbridge) Vboot UV Shut-down voltage threshold Hysteresis on Vboot Leakage current on high voltage pins to GND (VBOOT = VBRIDGE = DRV_HI = 600 V) Consumption in active mode (VCC = Vboot, fsw = 100 kHz and 1 nF load on both driver outputs) Consumption in inhibition mode (VCC = Vboot) VCC current consumption in inhibition mode Vboot current consumption in inhibition mode 1. 2. 3. 4. 5. VCC_stup VCC_shtdwn VCC_hyst Vboot_stup Vboot_shtdwn Vboot_shtdwn IHV_LEAK ICC1 ICC2 ICC3 ICC4 8.0 7.3 0.3 8.0 7.3 0.3 - - - - - 8.9 8.2 0.7 8.9 8.2 0.7 5 4 250 200 50 9.9 9.1 - 9.9 9.1 - 40 5 400 - - V V V V V V mA mA mA mA mA VIN RIN VIN IIN+ IIN- - - 2.3 - - - 200 - 5 - 0.8 - - 25 2.0 V kW V mA mA tON tOFF tr tf Dt DT tPW1 tPW2 - - - - - 65 - 20 100 100 85 35 20 100 - - 170 170 160 75 35 190 50 - ns ns ns ns ns ns ns ns IDRVsource IDRVsink ROH ROL VDRV_H VDRV_L - - - - - - 250 500 30 10 0.7 0.2 - - 60 20 1.6 0.6 mA mA W W V V Symbol Min Typ Max Units
Parameter guaranteed by design. Turn-off propagation delay @ Vbridge = 600 V is guaranteed by design. See characterization curve for Dt parameters variation on the full range temperature. Version B integrates a dead time in order to prevent any cross conduction between DRV_HI and DRV_LO. See timing diagram of Figure 10. Timing diagram definition see: Figure 7, Figure 8 and Figure 9.
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NCP5106A, NCP5106B
IN_HI IN_LO
DRV_HI DRV_LO
Figure 5. Input/Output Timing Diagram (A Version)
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 6. Input/Output Timing Diagram (B Version)
IN_HI (IN_LO) ton
50% tr 90%
50% tf 90% 10%
toff
DRV_HI (DRV_LO)
10%
Figure 7. Propagation Delay and Rise / Fall Time Definition
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NCP5106A, NCP5106B
IN_LO & IN_HI
50% ton_HI
50% toff_HI Delta_t 10% 90%
DRV_HI ton_LO
Delta_t
toff_LO DRV_LO 10% Matching Delay 1 = ton_HI - ton_LO Matching Delay 2 = toff_LO - toff_HI
90%
Figure 8. Matching Propagation Delay (A Version)
IN_HI
50%
50% toff_HI
ton_HI 90% DRV_HI 10% Matching Delay1=ton_HI-ton_LO IN_LO 50% toff_LO 90% DRV_LO 10% Matching Delay2=toff_HI-toff_LO 50%
ton_LO
Figure 9. Matching Propagation Delay (B Version)
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NCP5106A, NCP5106B
IN_HI
IN_LO
DRV_HI
DRV_LO Internal Deadtime Internal Deadtime
Figure 10. Input/Output Cross Conduction Output Protection Timing Diagram (B Version)
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NCP5106A, NCP5106B
CHARACTERIZATION CURVES
140 TON, PROPAGATION DELAY (ns) 120 100 80 60 40 20 0 TON Low Side TON, PROPAGATION DELAY (ns) TON High Side 140 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 TON Low Side
TON High Side
10
12
14 16 VCC, VOLTAGE (V)
18
20
Figure 11. Turn ON Propagation Delay vs. Supply Voltage (VCC = VBOOT)
140 TOFF, PROPAGATION DELAY (ns) 120 100 80 60 40 20 0 TOFF High Side TOFF Low Side TOFF, PROPAGATION DELAY (ns) 140 120 100 80 60 40 20 0 -40
Figure 12. Turn ON Propagation Delay vs. Temperature
TOFF Low Side TOFF High Side
10
12
14 16 VCC, VOLTAGE (V)
18
20
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
Figure 13. Turn OFF Propagation Delay vs. Supply Voltage (VCC = VBOOT)
140 TOFF PROPAGATION DELAY (ns) TON, PROPAGATION DELAY (ns) 120 100 80 60 40 20 0 160 140 120 100 80 60 40 20 0 0
Figure 14. Turn OFF Propagation Delay vs. Temperature
0
10
20
30
40
50
10
20
30
40
50
BRIDGE PIN VOLTAGE (V)
BRIDGE PIN VOLTAGE (V)
Figure 15. High Side Turn ON Propagation Delay vs. VBRIDGE Voltage
Figure 16. High Side Turn OFF Propagation Delay vs. VBRIDGE Voltage
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NCP5106A, NCP5106B
CHARACTERIZATION CURVES
160 140 TON, RISETIME (ns) TON, RISETIME (ns) 120 100 80 60 40 20 0 10 12 tr Low Side tr High Side 140 120 100 80 60 40 20 20 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 tr High Side tr Low Side
14 16 VCC, VOLTAGE (V)
18
Figure 17. Turn ON Risetime vs. Supply Voltage (VCC = VBOOT)
80 70 TOFF, FALLTIME (ns) TOFF, FALLTIME (ns) 60 50 40 30 20 10 0 10 tf High Side tf Low Side 70 60 50 40 30 20 10 14 16 VCC, VOLTAGE (V) 18 20 0 -40
Figure 18. Turn ON Risetime vs. Temperature
tf High Side
tf Low Side
12
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
Figure 19. Turn OFF Falltime vs. Supply Voltage (VCC = VBOOT)
PROPAGATION DELAY MATCHING (ns) 20 200 180 15 DEAD TIME (ns) 160 140 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 0 -40
Figure 20. Turn OFF Falltime vs. Temperature
10
5
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 21. Propagation Delay Matching Between High Side and Low Side Driver vs. Temperature http://onsemi.com
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Figure 22. Dead Time vs. Temperature
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
1.4 LOW LEVEL INPUT VOLTAGE THRESHOLD (V) 10 12 14 16 18 20 1.2 1 0.8 0.6 0.4 0.2 0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
VCC, VOLTAGE (V)
Figure 23. Low Level Input Voltage Threshold vs. Supply Voltage (VCC = VBOOT)
2.5 HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) 2 HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) 2.5 2.0 1.5 1.0 0.5 0.0 -40
Figure 24. Low Level Input Voltage Threshold vs. Temperature
1.5 1
0.5 0
10
12
14 16 VCC, VOLTAGE (V)
18
20
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 25. High Level Input Voltage Threshold vs. Supply Voltage (VCC = VBOOT)
4 LOGIC "0" INPUT CURRENT (mA) LOGIC "0" INPUT CURRENT (mA) 3.5 3 2.5 2 1.5 1 0.5 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5
Figure 26. High Level Input Voltage Threshold vs. Temperature
0 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 27. Logic "0" Input Current vs. Supply Voltage (VCC = VBOOT)
Figure 28. Logic "0" Input Current vs. Temperature
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NCP5106A, NCP5106B
CHARACTERIZATION CURVES
8 LOGIC "1" INPUT CURRENT (mA) LOGIC "1" INPUT CURRENT (mA) 10 12 14 16 VCC, VOLTAGE (V) 18 20 7 6 5 4 3 2 1 0 10 8 6 4 2 0 -40
-20
0
20
40
60
80
100
120
Figure 29. Logic "1" Input Current vs. Supply Voltage (VCC = VBOOT)
1 LOW LEVEL OUTPUT VOLTAGE (V) LOW LEVEL OUTPUT VOLTAGE THRESHOLD (V) 0.8 0.6 0.4 0.2 0 1.0 0.8 0.6 0.4 0.2 0.0 -40
Figure 30. Logic "1" Input Current vs. Temperature
TEMPERATURE (C)
10
12
14 16 VCC, VOLTAGE (V)
18
20
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
Figure 31. Low Level Output Voltage vs. Supply Voltage (VCC = VBOOT)
1.6 HIGH LEVEL OUTPUT VOLTAGE (V) HIGH LEVEL OUTPUT VOLTAGE THRESHOLD (V) 1.6
Figure 32. Low Level Output Voltage vs. Temperature
1.2
1.2
0.8
0.8
0.4
0.4
0 10
12
14 16 VCC, VOLTAGE (V)
18
20
0.0 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 33. High Level Output Voltage vs. Supply Voltage (VCC = VBOOT)
Figure 34. High Level Output Voltage vs. Temperature
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NCP5106A, NCP5106B
CHARACTERIZATION CURVES
400 OUTPUT SOURCE CURRENT (mA) 350 300 250 200 150 100 50 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 Isrc Low Side Isrc High Side OUTPUT SOURCE CURRENT (mA) 400 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 100 120 Isrc Low Side Isrc High Side
TEMPERATURE (C)
Figure 35. Output Source Current vs. Supply Voltage (VCC = VBOOT)
600 OUTPUT SINK CURRENT (mA) Isink High Side OUTPUT SINK CURRENT (mA) 500 400 300 200 100 0 10 Isink Low Side 500 400 300 200 100 0 -40 600
Figure 36. Output Source Current vs. Temperature
Isink High Side
Isink Low Side
12
14
16
18
20
-20
0
20
40
60
80
100
120
VCC, VOLTAGE (V)
TEMPERATURE (C)
Figure 37. Output Sink Current vs. Supply Voltage (VCC = VBOOT)
HIGH SIDE LEAKAGE CURRENT ON HV PINS TO GND (mA) 0.2 0.16 0.12 0.08 0.04 0 20 LEAKAGE CURRENT ON HIGH VOLTAGE PINS (600 V) to GND (mA)
Figure 38. Output Sink Current vs. Temperature
15
10
5
0
100
200
300
400
500
600
0 -40
-20
0
20
40
60
80
100
120
HV PINS VOLTAGE (V)
TEMPERATURE (C)
Figure 39. Leakage Current on High Voltage Pins (600 V) to Ground vs. VBRIDGE Voltage (VBRIGDE = VBOOT = VDRV_HI) http://onsemi.com
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Figure 40. Leakage Current on High Voltage Pins (600 V) to Ground vs. Temperature (VBRIDGE = VBOOT = VDRv_HI = 600 V)
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
100 VBOOT CURRENT SUPPLY (mA) 0 4 8 12 16 20 VBOOT SUPPLY CURRENT (mA) 80 60 40 20 0 100 80 60 40 20 0 -40
-20
0
20
40
60
80
100
120
VBOOT, VOLTAGE (V)
TEMPERATURE (C)
Figure 41. VBOOT Supply Current vs. Bootstrap Supply Voltage
240 VCC SUPPLY CURRENT (mA) VCC CURRENT SUPPLY (mA) 200 160 120 80 40 0 400
Figure 42. VBOOT Supply Current vs. Temperature
300
200
100
0
4
8
12
16
20
0 -40
-20
0
20
40
60
80
100
120
VCC, VOLTAGE (V)
TEMPERATURE (C)
Figure 43. VCC Supply Current vs. VCC Supply Voltage
10.0 UVLO STARTUP VOLTAGE (V) 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 -40 -20 0 20 40 60 80 100 120 VBOOT UVLO Startup UVLO SHUTDOWN VOLTAGE (V) VCC UVLO Startup 9.0 8.8 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 -40
Figure 44. VCC Supply Current vs. Temperature
VCC UVLO Shutdown
VBOOT UVLO Shutdown
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 45. UVLO Startup Voltage vs. Temperature
Figure 46. UVLO Shutdown Voltage vs. Temperature
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NCP5106A, NCP5106B
CHARACTERIZATION CURVES
25 CLOAD = 1 nF/Q = 15 nC 20 15 10 5 RGATE = 0 R to 22 R 0 0 100 200 300 400 500 600 ICC+ IBOOT CURRENT SUPPLY (mA) 40 35 30 25 20 15 10 5 0 0 100 200 300 400 500 SWITCHING FREQUENCY (kHz) 600 RGATE = 22 R RGATE = 10 R CLOAD = 2.2 nF/Q = 33 nC RGATE = 0 R
ICC+ IBOOT CURRENT SUPPLY (mA)
SWITCHING FREQUENCY (kHz)
Figure 47. ICC1 Consumption vs. Switching Frequency with 15 nC Load on Each Driver @ VCC = 15 V
70 ICC+ IBOOT CURRENT SUPPLY (mA) ICC+ IBOOT CURRENT SUPPLY (mA) 60 50 40 30 20 10 0 0 100 200 300 400 500 600 RGATE = 22 R RGATE = 10 R CLOAD = 3.3 nF/Q = 50 nC RGATE = 0 R 120
Figure 48. ICC1 Consumption vs. Switching Frequency with 33 nC Load on Each Driver @ VCC = 15 V
CLOAD = 6.6 nF/Q = 100 nC 100 80 60 40 20 0
RGATE = 0 R
RGATE = 10 R
RGATE = 22 R
0
100
SWITCHING FREQUENCY (kHz)
200 300 400 500 SWITCHING FREQUENCY (kHz)
600
Figure 49. ICC1 Consumption vs. Switching Frequency with 50 nC Load on Each Driver @ VCC = 15 V
0 NEGATIVE PULSE VOLTAGE (V) NEGATIVE PULSE VOLTAGE (V) -5 -10 -15 -20 -25 -30 -35 0 100 200 300 400 500 NEGATIVE PULSE DURATION (ns) 600 125C -40C 25C 0 -5 -10 -15 -20 -25 -30 -35 0
Figure 50. ICC1 Consumption vs. Switching Frequency with 100 nC Load on Each Driver @ VCC = 15 V
-40C
25C
125C
100 200 300 400 500 NEGATIVE PULSE DURATION (ns)
600
Figure 51. NCP5106A, Negative Voltage Safe Operating Area on the Bridge Pin
Figure 52. NCP5106B, Negative Voltage Safe Operating Area on the Bridge Pin
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NCP5106A, NCP5106B
APPLICATION INFORMATION
Negative Voltage Safe Operating Area
When the driver is used in a half bridge configuration, it is possible to see negative voltage appearing on the bridge pin (pin 6) during the power MOSFETs transitions. When the high-side MOSFET is switched off, the body diode of the low-side MOSFET starts to conduct. The negative voltage applied to the bridge pin thus corresponds to the forward voltage of the body diode. However, as pcb copper tracks and wire bonding introduce stray elements (inductance and capacitor), the maximum negative voltage of the bridge pin will combine the forward voltage and the oscillations created by the parasitic elements. As any CMOS device, the deep negative voltage of a selected pin can inject carriers into the substrate, leading to an erratic behavior of the concerned component. ON Semiconductor provides characterization data of its half-bridge driver to show the maximum negative voltage the driver can safely operate with. To prevent the negative injection, it is the designer duty to verify that the amount of negative voltage pertinent to his/her application does not exceed the characterization curve we provide, including some safety margin. In order to estimate the maximum negative voltage accepted by the driver, this parameter has been characterized over full the temperature range of the component. A test fixture has been developed in which we purposely negatively bias the bridge pin during the freewheel period of a buck converter. When the upper gate voltage shows signs of an erratic behavior, we consider the limit has been reached. Figure 51 (or 52), illustrates the negative voltage safe operating area. Its interpretation is as follows: assume a negative 10 V pulse featuring a 100 ns width is applied on the bridge pin, the driver will work correctly over the whole die temperature range. Should the pulse swing to -20 V, keeping the same width of 100 ns, the driver will not work properly or will be damaged for temperatures below 125C.
* If the negative pulse characteristic (negative voltage
Summary:
level & pulse width) is above the curves the driver runs in safe operating area. * If the negative pulse characteristic (negative voltage level & pulse width) is below one or all curves the driver will NOT run in safe operating area. Note, each curve of the Figure 51 (or 52) represents the negative voltage and width level where the driver starts to fail at the corresponding die temperature. If in the application the bridge pin is too close of the safe operating limit, it is possible to limit the negative voltage to the bridge pin by inserting one resistor and one diode as follows:
Vcc D2 U1 NCP5106A VCC IN_HI IN_LO GND MUR160 8 7 6 5 R1 10R M2 C1 100n Vbulk
1 IN_Hi IN_LO 0 2 3 4
M1
VBOOT DRV_HI BRIDGE DRV_LO
D1 MUR160 0
Figure 53. R1 and D1 Improves the Robustness of the Driver
R1 and D1 should be placed as close as possible of the driver. D1 should be connected directly between the bridge pin (pin 6) and the ground pin (pin 4). By this way the negative voltage applied to the bridge pin will be limited by D1 and R1 and will prevent any wrong behavior.
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NCP5106A, NCP5106B
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-X- A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5106A, NCP5106B
PACKAGE DIMENSIONS
8 LEAD PDIP CASE 626-05 ISSUE L
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040
8
5
-B-
1 4
F
NOTE 2
-A-
L
C -T-
SEATING PLANE
J N D K
M
M TA B
H
G 0.13 (0.005)
M M
The product described herein is covered by U.S. patents: 6,097,075; 7,176,723; 6,362,067. There may be some other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5106/D

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